Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■RED WOOD chipset
Applicable PC-9821Np, Ns, Ne2, Nd, Es, Ld, Lt, Nf, Nm, PC-9801NL/A
Chip RED WOOD
Explanation o RED WOOD is a power management controller made by PICO|POWER.
o In the PC-9821Nf, the GOLDEN GATE chipset is used together with the RED WOOD chipset, also made by PICO|POWER.
o The RED WOOD chipset uses the same I/O addresses 0900h and 0906h as the
GOLDEN GATE chipset. Access to these I/O addresses is made to the RED WOOD
chipset for word access and to the GOLDEN GATE chipset for byte access.
Therefore, access to the RED WOOD chipset must always be word access.
o RED WOOD means "Redwood" in English.
Related I/O 0900h (BYTE)
I/O 0906h (BYTE)
F8E8:0004h bit 1
I/O 088Eh
Name Power management controller [INDEX] read back
Target PC-9821Np, Ns, Ne2, Nd, Es, Ld, Lt, Nf, Nm, PC-9801NL/A
Undocumeted
Function
[READ]
Bits 15-0: Power management controller register number
[WRITE] None
Explanation o Reads the register number of the power management controller currently selected by I/O 0900h.
o Used in the processing of INT 17h
Related I/O 0900h
I/O 0900h (WORD)
Name Power Management Controller [INDEX]
Target PC-9821Np, Ns, Ne2, Nd, Es, Ld, Lt, Nf, Nm, PC-9801NL/A
Undocumented
Chip REDWOOD1, REDWOOD2
Function
[READ] None
[WRITE]
bit 15-0: Power Management Controller Register
* Specify the register number to be operated with I/O 0906h
Explanation o Pair with I/O 0906h to perform two-stage I/O operation
Related I/O 088Eh
I/O 0906h
I/O 0906h (WORD)
Name Power Management Controller [DATA]
Target PC-9821Np, Ns, Ne2, Nd, Es, Ld, Lt, Nf, Nm, PC-9801NL/A
Undocumented
Chip REDWOOD1, REDWOOD2
Function
[READ/WRITE]
bit 15-0: Resume control
----------------+--------------------------------------------------
Register number |
|R/W| Contents
------------+---+--------------------------------------------------
0000h |R/W| PMC Clock Control Register
------------+---+--------------------------------------------------
0001h |R/W| Power Management Status Register
| | bit 15-13: Power Management Mode
| | bit 12: Reserved
| | bit 11: WAKE1STATUS
| | bit 10: WAKE0STATUS
| | bit 9: RESUME
| | bits 8-4: PMISRC
| | bit 3: ACPWR
| | 1 = AC adapter is connected
| | 0 = AC adapter is not connected
| | bits 2-0: WAKESRC
| | * Controls the power supply.
------------+---+--------------------------------------------------
0002h | R | Activity Source Register
0003h |R/W| Primary Activity Register
0004h |R/W| PMI Mask Register
0005h |R/W| Heat Regulator Control Register
0006h |R/W| PMI Mask and Control Register
0007h |R/W| General Purpose Control Register
| | bit 11: GPIO DATA3
| | 1 = Battery capacity remaining
| | 0 = Low battery
| | * For PC-9800 series, GPIO DATA3 is used as low battery status
------------+---+--------------------------------------------------
0008h |R/W| Stop Clock Control Register
0009h |R/W| Fully-On Mode Power Control Register
000Ah |R/W| Doze Mode Power Control Register
000Bh |R/W| Sleep Mode Power Control Register
000Ch |R/W| Suspend Mode Power Control Register
000Dh |R/W| Timer Register
000Eh |R/W| PMC Miscellaneous Control Register1
000Fh |R/W| Reserved
0010h |R/W| GP Counter/Timer Register
0011h |R/W| GP Timer Counter Register
0012h |R/W| Debounce Control Register
0013h |R/W| PMC Miscellaneous Control Register2
------------+---+--------------------------------------------------
0014h |R/W| Optional GPIO Control Register
| | Keyboard selection ■ [PC-9821Np/Ns/Nf]
| | bit 15-2: Unknown
| | bit 1: GPIO A 1
| | Keyboard selection
| | 1 = External keyboard
| | 0 = Built-in keyboard
| | * External keyboard via docking station
| | Set when using a board.
| | Related 0000:045Dh bit 1
| | I/O 881Eh bit 2
| | bit 0: unknown
------------+---+---------------------------------------------------
0015h |R/W| Leakage Control Register
0016h |R/W| Reserved
0017h |R/W| Reserved
0018h |R/W| Reserved
0019h |R/W| Secondary Activity Mask Register
001Ah |R/W| Additional Activity Source Register
001Ch |R/W| Additional Secondary Activity Control Register
001Dh |R/W| Additional PMI Mask Register
001Eh |R/W| Miscellaneous Control Register
------------+---+--------------------------------------------------
0020h |R/W| Programmable Range Compare Register 0
0021h |R/W| Programmable Range Compare Register 0
| | * In the PC-9800 series, this is used to test the CPU's built-in cache by
| | monitoring memory space 008000-00BFFFh. Normally not used.
0022h |R/W| Programmable Range Compare Register 1
0023h |R/W| Programmable Range Compare Register 1
| | * In the PC-9821Ld and PC-9801NL/A, the lower 10 bits of the I/O space are
| | normally used to monitor access to I/O at 010001110b (notebook related).
0024h |R/W| Programmable Range Compare Register 2
0025h |R/W| Programmable Range Compare Register 2
| | * In the PC-9800 series, the lower 10 bits of the I/O space are usually
| | used to monitor access to 101000001b (printer).
0026h |R/W| Programmable Range Compare Register 3
0027h |R/W| Programmable Range Compare Register 3
| | * Not usually used in the PC-9800 series.
------------+---+--------------------------------------------------
0028h |R/W| Programmable Timeout Timer Register 0
| | * Used to set the standby mode in the PC-9800 series
0029h |R/W| Programmable Timeout Timer Register 1
| | * Not usually used in the PC-9800 series.
002Ah |R/W| Programmable Timeout Timer Register 2
| | * Not normally used on the PC-9800 series.
002Bh |R/W| Programmable Timeout Timer Register 3
| | * Not normally used on the PC-9800 series.
002Ch |R/W| Programmable Timeout Timer Source Register 1
002Dh |R/W| Programmable Timeout Timer Source Register 2
002Eh |R/W| Programmable Timeout Timer Source Register 3
002Fh |R/W| Programmable Timeout Timer Source Register 4
------------+---+--------------------------------------------------
0030h |R/W| Unknown
0031h |R/W| Unknown
0032h |R/W| Unknown
------------+---+--------------------------------------------------
0100h |R/W| Power-On Register
| | bit 15-13: Reserved
| | bit 12: Reserved
| | bit 11: EXTRTC
| | bit 10: Reserved
| | bit 9: MISCF2
| |
| | ■[PC-9821Ld, PC-9801NL/A]
| | bit 8: MISCF1
| | 1 = PC-9821Ld
| | 0 = PC-9801NL/A
| | * For PC-9821Ld and PC-9801NL/A, MISCF1 is used to identify the model.
| | Related 0000:045Ch bit 6,5
| | 0000:0597h
| | bit 7: MISCF0
| | 1 = 2MB of installed memory
| | 0 = 0MB of installed memory
| | * On the PC-9821Ld and PC-9801NL/A, MISCF0 is used
| | to identify the amount of memory installed on the board.
| |
| | ■[PC-9821Ns･Ne2･Nd]
| | bit 8,7: MISCF1,0
| | 11b = 4MB of installed memory
| | 10b = 4MB of installed memory
| | 01b = 4MB of installed memory
| | 00b = 0MB of installed memory
| | * For PC-9821Ns･Ne2･Nd, MISCF1,0 are used
| | to identify the amount of memory installed on the board.
| |
| | bit 6: Reserved
| | bit 5: Reserved
| | bit 4: CPUMODESEL
| | bit 3: Reserved
| | bit 2: Reserved
| | bit 1: 386SEL
| | bit 0: REDWOODSEL
------------+---+--------------------------------------------------
0101h |R/W| Non-Cacheable Region 1 Register
| | bit 15-3: Non-Cacheable Region 1 Starting Address
| | * Specifies bits 27-15 of the starting address of the non-cacheable region
| | bit 2,1: Non-Cacheable Region 1 Block Size
| | 11b = 256KB
| | 10b = 128KB
| | 01b = 64KB
| | 00b = 32KB
| | bit 0: Enable Non-Cacheable Region 1
| | 1 = Enable
| | 0 = Disable
| | * In the PC-9800 series, this is used to specify 32KB from physical memory D8000h as a non-cacheable region
0102h |R/W| Non-Cacheable Region 2 Register
| | * Not normally used in the PC-9800 series
0103h |R/W| SYS Miscellaneous Control Register 1
0104h |R/W| SYS Miscellaneous Control Register 2
0105h | | 0000h written in ITF
0106h | | 0000h written in ITF
0110h |R/W| REDWOOD 1 Pin Select Register 1
0111h |R/W| REDWOOD 1 Pin Select Register 2
0112h |R/W| REDWOOD 1 Pin Select Register 3
0118h |R/W| Reserved
0180h |R/W| Burst Bus Control Register
------------+---+--------------------------------------------------
0200h |R/W| Shadow RAM Read Enable Control Register
0201h |R/W| Shadow RAM Write Enable Control Register
| | bit 15-13: Reserved
| | bit 12-0: LMEMRDEN12-0
| | 1 = Enable
| | 0 = Disable
| | * Enables/disables reading and writing of the shadow RAM in each specified range.
------------+---+---------------------------------------------------
0202h |R/W| Bank 0 Control Register
0203h |R/W| Bank 1 Control Register
0204h |R/W| Bank 0/1 Timing Control Register
0205h |R/W| Bank 2 Control Register
0206h |R/W| Bank 3 Control Register
0207h |R/W| Bank 2/3 Timing Control Register
0208h |R/W| Bank 4 Control Register
0209h |R/W| Bank 5 Control Register
020Ah |R/W| Bank 4/5 Timing Control Register
------------+---+--------------------------------------------------
020Bh |R/W| DRAM Configuration Register 1
020Ch |R/W| DRAM Configuration Register 2
020Dh |R/W| DRAM Configuration Register 3
020Eh |R/W| DRAM Configuration Register 4
020Fh |R/W| DRAM Configuration Register 5
| | bit 15-10: ENE8ROMCS-ENC0ROMCS
| | bit 9: Bank RAM window
| | 1 = Bank RAM access allowed
| | 0 = Bank RAM access prohibited
| | * Used to separate bank RAM when accessing PCMCIA memory window, etc.
| | bit 8: Unknown
| | bit 7: Unknown
| | bits 6-2: Bank ROM control
| | 00100b = 98NOTE MENU #0
| | 00101b = 98NOTE MENU #1
| | 00110b = 98NOTE MENU #2
| | 00111b = 98NOTE MENU #3
| | 01001b = JEIDA BIOS
| | 01011b = IDE HDD initialization routine, etc.?
| | 01100b = RAM drive BIOS, etc.
| | 01101b = Routine to switch to Note menu, etc.
| | 10100b = BIOS ROM #00h (E8000-E9FFFh)
| | :
| | :
| | 11111b = BIOS ROM #0bh (F0000-FFFFFh)
| | bit 1: FLASHENB
| | bit 0: ITF mapping
| | 1 = BIOS
| | 0 = ITF
| | * Selects whether to map ITF to the space F800:0000-7FFFh.
------------+---+--------------------------------------------------
0210h |R/W| Bank RAM control
| | bit 15-0: Bank RAM address
| | 0050h = Setup data
| | 0051h = RAM drive ID data
| | 0052h = Resume work area
| | 0053h = Menu patch data
| | 0054h = TEXT VRAM save
| | 0055h = TEXT attribute save
| | 0056h = Resume work (graphics related)
| | 0057h = Unused
| | 0058-005Fh = RAM drive data
| | 0068-007Fh = RAM drive data
| | ??80-??FFh = RAM drive data?
------------+---+--------------------------------------------------
0211h |R/W| Read the dedicated additional memory capacity?
| | bit 15-9: Unknown
| | bit 8-2: Dedicated additional memory capacity
| | ???0000b = 0MB
| | ???0001b = 2MB
| | ???0010b = 4MB
| | ???0011b = 6MB
| | ???0100b = 8MB
| | ???0101b = 10MB
| | ???0110b = 16MB
| | ???0111b = 18MB
| | ???1??0b = 16MB
| | ???1??1b = 18MB
| | bit 1,0
------------+---+--------------------------------------------------
0300h |R/W| AT Miscellaneous Control Register 1
| | ■[PC-9821Np･Ns･Nf]
| | bit 15-13: Unknown
| | bit 12: Notebook expansion I/O box flag
| | 1 = None
| | 0 = Yes
| | Related 0000:045Ch bit 2
| | bit 11-0: Unknown
0301h |R/W| AT Miscellaneous Control Register 2
0303h |R/W| Modular Clock Control Register
0304h | | Unknown
------------+---+--------------------------------------------------
0350h |R/W| Primary Activities IRQ Mask Register
0351h |R/W| PMI Trigger Source IRQ Active Register
0352h |R/W| PMI Trigger Source IRQ Mask Register
0353h |R/W| IRQ Secondary Activity Enable Register
------------+---+--------------------------------------------------
0500h | R | 8254 Counter0 Shadow Register1
0501h | R | 8254 Counter0 Shadow Register2
0502h | R | 8254 Counter1 Shadow Register1
0503h | R | 8254 Counter1 Shadow Register2
0504h | R | 8254 Counter2 Shadow Register1
0505h | R | 8254 Counter2 Shadow Register2
0506h | R | 8254 Counter0 Shadow Register3
0507h | R | 8254 Counter1 Shadow Register3
0508h | R | 8254 Counter2 Shadow Register3
| | * Register for reading 8254TCU settings
| | Related I/O 0071h
| | I/O 0073h
| | I/O 0075h
| | I/O 0077h
------------+---+---------------------------------------------------
0520h | R | 8259 Interrupt Controller Shadow Register1
0521h | R | 8259 Interrupt Controller Shadow Register2
0522h | R | 8259 Interrupt Controller Shadow Register3
0523h | R | 8259 Interrupt Controller Shadow Register4
0524h | R | 8259 Interrupt Controller Shadow Register5
0525h | R | 8259 Interrupt Controller Shadow Register6
0526h | R | 8259 Interrupt Controller Shadow Register7
0527h | R | 8259 Interrupt Controller Shadow Register8
0528h | R | 8259 Interrupt Controller Shadow Register9
052Ah | R | 8259 Interrupt Controller Shadow Register10
052Bh | R | 8259 Interrupt Controller Shadow Register11
| | * Register for reading 8259PIC settings
------------+---+--------------------------------------------------
* Reads and writes the register specified by I/O 0900h
Explanation o Pairs with I/O 0900h to perform two-stage I/O operations.
Related I/O 0900h (WORD)